library ieee;
use ieee.std_logic_1164.all;

entity decode is 
	port(InstrD, Wd3: in std_logic_vector(31 downto 0);
		 A3: in std_logic_vector(4 downto 0);
		 clk, RegWrite: in std_logic;
		 SignImmD, RD1D, RD2D: out std_logic_vector(31 downto 0);
		 RtD, RdD: out std_logic_vector(4 downto 0));
end entity;

architecture decode_arch of decode is

	component regfile
		port(ra1, ra2, wa3 : in std_logic_vector(4 downto 0);
			 clk, we3 : in std_logic;
			 wd3	: in std_logic_vector(31 downto 0);
			 rd1, rd2 : out std_logic_vector(31 downto 0));
	end component;
	
	component signext
		port(a : in std_logic_vector(15 downto 0);
        	  y : out std_logic_vector(31 downto 0));
	end component;
	
	begin
	regfile_D: regfile port map (ra1=>InstrD(25 downto 21),
								  ra2=>InstrD(20 downto 16),
								  wa3=>A3,clk=>clk,we3=>RegWrite,wd3=>Wd3,rd1=>RD1D,rd2=>RD2D);
	signext_D: signext port map (a=>InstrD(15 downto 0), y=>SignImmD);
	RtD <= InstrD(20 downto 16);
	RdD <= InstrD(15 downto 11);
	
end architecture;
